Nanometer CMOS ICs by Harry J.M. Veendrick

Author:Harry J.M. Veendrick
Language: eng
Format: epub
Publisher: Springer International Publishing, Cham

Under the influence of heat generated by Joule heating, the polycrystalline state can be changed into an amorphous state and back. Each of these states corresponds to a different value of electrical resistivity representing a logic one and logic zero. When heated above melting point ( ≈ 650 ∘C), the chalcogenide alloy totally loses its crystalline structure. In the cell in Fig. 6.48 only a small programmable volume of the material is locally heated to above its melting point. This heat can be supplied by a current pulse through the heater. When rapidly cooled, the chalcogenide material is locked into its amorphous high-impedance state. By heating the material above its crystallisation but below its melting temperature the cell switches back to its low-impedance crystalline state. The difference in impedance between the two states is between one and two orders of magnitude. During a read operation, a voltage is applied to the cell and the read current is measured against the read current of an identical reference cell with a fixed logic state. Similar to all memories that use a reference cell during reading, this cell must be placed well within the memory array to reduce array edge effects, or must be surrounded by dummy cells. In sub-50 nm technologies, the use of reference cells is becoming more and more difficult due to variability. Instead of using reference cells, a dedicated circuit for creating the reference current is becoming more and more common. This reference current generator provides the optimum reference current for fast and reliable read operations, including aging effects.

Today’s PRAM complexity is still far behind that of DRAM and SRAM, but due to the extending application areas with limited power budgets, particularly in hand-held devices, there is more pressure to develop a real non-volatile RAM. Volume production of the first commercial PRAM was announced for the second half of 2007. Examples of PRAM designs can be found in [46, 47] and [48]. PRAMs are currently commercially available and seen as the most promising successor of NOR-flash [49, 50]. In 2008 the first multi-level 256 Mb PRAM prototypes were presented. While the ‘0’ and the ‘1’ were represented by the fully amorphous and fully crystalline state, the two additional states were represented by different levels of partial crystallisation [51].

Many other non-volatile techniques are currently in basic R&D phase. There are two that look promising and which I only want to mention here. The first one is the resistive RAM (RRAM or ReRAM) , a memory, whose operation is also based on resistance change. It consists of a metal/perovskite-oxide/metal sandwich structure, in which a reversible resistance switching behaviour can be triggered by the application of short voltage pulses [52, 53]. It has been shown that RRAM can switch fast ( < 0.3 ns) [54] and can be used in low-power applications [55]. A 32 Gb demonstrator in 24 nm technology has been presented in 2013 [56]. Finally, the second one is the conductive bridging memory (CBRAM) , in which the cell consists of a thin electrolyte layer, sandwiched between two electrodes. The logic state of a cell is defined by deposition or removal of metal, e.

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